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  • Pine Yan, Aditya Kher, Jerry Chen, Ko Ihara, Yu Ching Li, Prabha Krishnaswami ,Aswin Vijaya Varma, “Realizing Faster Simulations/Diagnosis with VCS’ New Parallel Simulation and UFE Technology”, Proceedings from SNUG in San Jose, India March 2018
  • David Hsu, Aditya Kher, Harsh Chilwal, “Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily”, April Webinar on
  • A. Kher “Can You Tell Your ISO from LS? – A Methodology for Low Power Debug”, proceedings from Silicon Valley SNUG, Mar 2013
  • J. Liu, H. Vardhan, A. Kher, J. Choi, “Low Power Veri cation with UPF: Principle and Practice”, Proceedings from DVCon in San Jose, CA, Mar 2010
  • J. Liu, H. Vardhan, A. Kher, J. Choi, “Multi-Voltage Veri cation for High End Mobile Processor Design”, Proceedings from SNUG in Bangalore, India Aug 2009.
  • H. Jung, A. Kher, “SystemVerilog, VMM overcome WiMax veri cation challenges”, Chip Design Magazine, Aug 2009.
  • H. Jung, A. Kher, “Verifying Designs for Wireless-Broadband Applications Using SystemVerilog and Next Generation VMM” Proceedings from SNUG in Boston Aug 2008.
  • A. Kher, D. Khandage, “Hardware assisted veri cation using VMM – Case study of veri cation of Serial ATA host using co-emulation”, White Paper , Synopsys.