{"id":16,"date":"2011-05-30T23:22:50","date_gmt":"2011-05-30T23:22:50","guid":{"rendered":"http:\/\/kher.org\/blog\/?page_id=16"},"modified":"2022-02-22T03:11:14","modified_gmt":"2022-02-22T03:11:14","slug":"publications","status":"publish","type":"page","link":"https:\/\/kher.org\/blog\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"<ul>\n<li>Ramesh Narayanaswamy, Magnus Ekman, He Li, Ruohuang Zheng, Aaron Beddes, Aditya Kher, Rohit Narkar, &#8220;<strong>Large Scale IC Simulation Workload on ARM Server CPU<\/strong>&#8220;, Proceedings from NVIDIA GTC, 2022<\/li>\n<li>Pine Yan, Aditya Kher, Jerry Chen, Ko Ihara, Yu Ching Li, Prabha Krishnaswami ,Aswin Vijaya Varma, &#8220;<strong>Realizing Faster Simulations\/Diagnosis with VCS\u2019 New Parallel Simulation and UFE Technology<\/strong>&#8220;, <em>Proceedings from SNUG<\/em> in San Jose, India March 2018<\/li>\n<li>\n<div id=\"stcpDiv\">\n<div id=\"stcpDiv\">David Hsu, Aditya Kher, Harsh Chilwal, &#8220;<strong>Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily<\/strong>&#8220;, April Webinar on www.synopsys.com<\/div>\n<\/div>\n<\/li>\n<li>A. Kher &#8220;<strong>Can You Tell Your ISO from LS? &#8211; A Methodology for Low Power Debug<\/strong>&#8220;, proceedings from Silicon Valley SNUG, Mar 2013<\/li>\n<li>J. Liu, H. Vardhan, A. Kher, J. Choi et.al, &#8220;<strong>Low Power Veri\fcation with UPF: Principle and Practice<\/strong>&#8220;,<em> Proceedings from DVCon<\/em> in San Jose, CA, Mar 2010<\/li>\n<li>J. Liu, H. Vardhan, A. Kher, J. Choi et.al, &#8220;<strong>Multi-Voltage Veri\fcation for High End Mobile Processor Design<\/strong>&#8220;, <em>Proceedings from SNUG<\/em> in Bangalore, India Aug 2009.<\/li>\n<li>H. Jung, A. Kher, &#8220;<strong>SystemVerilog, VMM overcome WiMax veri\fcation challenges<\/strong>&#8220;, <em>Chip Design Magazine<\/em>, Aug 2009.<\/li>\n<li>H. Jung, A. Kher, &#8220;<strong>Verifying Designs for Wireless-Broadband Applications Using SystemVerilog and Next Generation VMM<\/strong>&#8221; <em>Proceedings from SNUG<\/em> in Boston Aug 2008.<\/li>\n<li>A. Kher, D. Khandage, &#8220;<strong>Hardware assisted veri\fcation using VMM &#8211; Case study of veri\fcation of Serial ATA host using co-emulation<\/strong>&#8220;, <em>White Paper , Synopsys<\/em>.<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Ramesh Narayanaswamy, Magnus Ekman, He Li, Ruohuang Zheng, Aaron Beddes, Aditya Kher, Rohit Narkar, &#8220;Large Scale IC Simulation Workload on ARM Server CPU&#8220;, Proceedings from NVIDIA GTC, 2022 Pine Yan, Aditya Kher, Jerry Chen, Ko Ihara, Yu Ching Li, Prabha Krishnaswami ,Aswin Vijaya Varma, &#8220;Realizing Faster Simulations\/Diagnosis with VCS\u2019 New Parallel Simulation and UFE Technology&#8220;, [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-16","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/pages\/16","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/comments?post=16"}],"version-history":[{"count":0,"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/pages\/16\/revisions"}],"wp:attachment":[{"href":"https:\/\/kher.org\/blog\/wp-json\/wp\/v2\/media?parent=16"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}